Monday, January 23, 2012

Using Xilinx ISE WebPack IDE With Digilent Basys2

Presently the bulk of our focus has laid in configuring a Linux machine to have the capacity to act as a development environment for the Digilent Basys2 Development board. In this document we will walk through the process of loading the basic default program into the Basys2 board.

This document assumes that you’ve erased your Basys2’s Electrically Erasable Programmable Read Only Memory (EEPROM) data or is running some design other than the design shipped with the Basys2. If this is not the case, to ensure that the Basys2 is erased you may execute the following while your Basys2 is connected via USB and is TURNED ON (make sure the power switch is in the ON position):
djtgcfg erase -d Basys2 -i 1

First and foremost we must start the Xilinx ISE WebPack Integrated Development Environment (IDE). To do so, assuming you have used the default installation path, you may execute (similar for different versions) the following:
cd /opt/Xilinx/13.3/ISE_DS/ISE/bin/lin/
./ise &
Minimizing the IDE and opening a web browser, we may goto the following location:,400,790&Prod=BASYS2

Locate the “Basys2 User Demo project” and download it.

In a terminal you may unzip the downloaded file using the unzip program:
This creates a pdf and a folder “Basys2UserDemo”. Let’s give focus back to the ISE WebPack IDE (Maximize it) and then select:

  1. File -> Open Project
    1. Browse to the unzipped folder location / “UncompiledBasys2UserDemo”
    2. Change “Files of Type” from “ISE Project Files (*.xise)” to “Old ISE Project Files (*.ise)”
    3. Select “Basys2UserDemo.ise” and Click “Open”
    4. When prompted to to mirgate the project, Click “Migrate Only”
  2. On the left there is a “Panel” called “Design” this may be toggled using “View -> Panels -> Design” though we will ensure this is checked and visible.
  3. Identify the Basys2UserDemo - Stuctural node in the Design Panel “Hierarchy,” select it and then right click on it.
  4. Select “Design Properties...”
  5. Ensure the following:
    1. Top-Level Source type: “HDL”
    2. Evaluation Development Board: “None Specified”
    3. Product Category: “All”
    4. Family: “Spartan 3E”
    5. Select “Device” to match if you have a 100K die or 250K die, 100K dies use XC3S100E and 250K dies use XC3S250E
    6. Package: “CP132”
    7. Speed: “-5”
    8. Click “OK”
  6. Identify the Basys2UserDemo - Stuctural node in the Design Panel “Hierarchy,” select it and then right click on it.
  7. Select “Implement Top-Module”
  8. Wait until all processing is complete...
  9. Identify “Generate Programming File” in the Design Panel under “Processes: Basys2UserDemo”, right click and select “Process Properties”
    1. Select “Startup Options” Category
    2. Ensure:
      1. FPGA Start-Up Clock: “JTAG Clock”
      2. Click “OK”
  10. Identify “Generate Programming File” in the Design Panel under “Processes: Basys2UserDemo”, right click and select “Run”
    1. This Generates a .BIT file which can be used to program the FPGA.
  11. From a terminal enter into the location enter the Basys2UserDemo/UncompiledBasys2UserDemo” folder and execute the following
    1. djtgcfg prog -d Basys2 -i 0 -f Basys2UserDemo.bit
    2. -i 0 : is the FPGA’s Random Access memory (RAM), this will not permanently load the User Demo to the Board.
    3. (Read the “Linux: Getting Started, Using Digilent Adept 2“ for more information if necessary)
Congratulations you should now have the user demo running on your Basys2! To Confirm this the 7-Segment displays on the bottom of the Basys2 will be counting from 0 to F in Hexadecimal and repeat.


  1. Thanks for writing this. I never erased the EEPROM and had all sorts of glitches trying to flash my own designs. Now everything's working as expected! And ISE running in Linux is so much faster than running in Windows 7, so that's a benefit too.

    1. Always glad to hear I've helped someone! Another satisfied geek.

  2. Thanks for your 3 tutorials, it helped me try ISE for the first time :-) Note: You might want to update your earlier tutorial to tell people that when downloading from the Xilinx site, the downloads page is now for Vivado that doesn't support FPGAs below Spartan-7! So now you need to switch to the "ISE" tab to download ISE instead of Vivado. I learnt that the hard way.

    1. I've updated the the link on the article for Installing ISE to point directly to the ISE tab. This way it's still just a click away. I haven't done this in a while, was everything else still valuable? Or did I miss any other steps when you went through it?

      Thanks for the feedback!

    2. Thanks! Direct download links often change, so to make it clearer, maybe you should say that the default Download page is for Vivado but Vivado doesn't support Spartan-3E, so you need to install ISE instead. Actually I had to overcome some problems in ISE related to my libstdc++ version, such as not using the libs that come with ISE and using the 32-bit version even though I'm on a 64-bit system, but it doesn't sound like others are having my same issues so maybe it's just a problem on my system and not worth updating your blog for.

  3. You writing article like a real nazi German electronic engineer sir.
    Good luck sir.

  4. Hi, i have an issue with the erase part of the board.
    Everytime i try to erase the board i get this error "ERROR: failed to initialize scan chain".
    Can you please help me